Best clock frequency search for FPGA-based design

摘要

Searching for desired clock frequency for integrated circuit-based design may receive timing result of a hardware synthesis job executed based on a code specifying hardware design. One or more different timing constraints specifying respective one or more different clock frequencies than used in the hardware synthesis job may be automatically generated without modifying the code. One or more instances of the hardware synthesis job to run with the respective one or more different timing constraints may be automatically spawned. The automatic generation and spawning may repeat until a termination criterion is met, and/or a desired successful timing constraint is identified for the hardware design from the different timing constraints based on whether the one or more instances of the hardware synthesis job met their respective timing constraints.