Unfolded decision-directed loop, architectures, apparatuses and systems including the same, and methods, algorithms and software for reducing latency in decision-directed loops

摘要

Unfolded adaptive/decision-directed loops and correction circuits therefor, architectures, apparatuses and systems including the same, and methods, algorithms and software for reducing latency in an adaptive and/or decision-directed loop. Disclosed embodiments advantageously reduce effects of loop latency, improve the accuracy of corrections in an adaptive loop, and minimize overhead and delays associated with such improvements.