发明名称 |
FPGA RAM BLOCKS OPTIMIZED FOR USE AS REGISTER FILES |
摘要 |
A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.
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申请公布号 |
US2013271180(A1) |
申请公布日期 |
2013.10.17 |
申请号 |
US201313898827 |
申请日期 |
2013.05.21 |
申请人 |
MICROSEMI SOC CORPORATION |
发明人 |
LANDRY JOEL;GREENE JONATHAN;PLANTS WILLIAM C.;FENG WENYI |
分类号 |
H03K19/177 |
主分类号 |
H03K19/177 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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