发明名称 DELTA RETIMING IN LOGIC SIMULATION
摘要 Aspects of the present invention are directed to improving the speed of event-driven simulation by manipulating delta delays in a system model to reduce delta cycle executions. The manipulation is performed in a manner that preserves delta cycle accurate timing on selected signals of the system, which may be of interest to a designer. Methods and systems are provided for identifying the signals of interest, and for determining portions of the design that may have delta delays retimed. Preserving the timing on the signals of interest ensures that race conditions and glitches present in the design on the signals of interest are still viewable by the designer. To reduce simulation time, delta delays may be moved from high activity signals to low activity signals, the total number of delta delays may be reduced, or a number of processes executed may be reduced.
申请公布号 US2013275112(A1) 申请公布日期 2013.10.17
申请号 US201213731604 申请日期 2012.12.31
申请人 MENTOR GRAPHICS CORPORATION;MENTOR GRAPHICS CORPORATION 发明人 KAKKAR SACHIN;RIES JOHN
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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