| 摘要 |
A connection for the fast analysis of packet headers by a circuit connected directly to the data bus, which transfers the packets. This circuit contains sub-circuits for the protocols headers analysis. Furthermore, the circuit contains a counter, which informs the sub-circuits about the data bus status. Each of the sub-circuits is equipped with the data input from the data bus, the input of the counter, the activating input, which determines the presence of the given protocol header in the packet, and with the input of the position of the header start in the packet. Further, each of the sub-circuits is equipped with a set of activating outputs, which determine the type of the next protocol header, and with the output of the position of the next header start. All sub-circuits, using the auxiliary logic circuits and multiplexers, are connected in the structure, which corresponds to the number and structure of the anticipated protocols in the packet. Chain thus created from sub-circuits is then in the same manner divided into branches based on the anticipated number of protocols, the headers of which are to be analyzed.
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