发明名称 MEMORY CONTROLLER, SEMICONDUCTOR STORAGE, AND DECODING METHOD
摘要 PROBLEM TO BE SOLVED: To achieve a memory controller which prevents increase in circuit scale without making its processing complicated.SOLUTION: A memory controller includes: an encoding unit which generates redundant data by performing error detection encoding on data to be written to a memory unit; n memory interfaces (n is an integer of 2 or greater) each having a first error correction decoding unit which reads out the data and the redundant data from the memory unit, and performs, on the readout data, first error correction decoding having first error correction capability; and less than n second error correction encoding unit(s) which performs second error correction decoding having second error correction capability that is higher than the first error correction capability. If the first error correction decoding on the readout data fails, an instruction for performing the second error correction decoding is given to the second error correction decoding unit(s). If the second error correction encoding unit(s) is not available, the readout data to be input is changed, and redecoding is performed using the first error correction decoding unit.
申请公布号 JP2013214212(A) 申请公布日期 2013.10.17
申请号 JP20120084274 申请日期 2012.04.02
申请人 TOSHIBA CORP 发明人 MORO SUKEYUKI;IWASAKI KIYOTAKA
分类号 G06F12/16;G11C29/42 主分类号 G06F12/16
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