| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory bus interface that balances between bus performance and a required number of bus signals.SOLUTION: A method and an apparatus for a memory bus interface 120 includes a read data strobe, includes a chip selection for delivering a chip selection signal that indicates when peripheral devices 130, 135 are activated, and provides communication between a host device and the peripheral devices. The interface also includes a differential clock pair for delivering a differential clock signal. The read data strobe is included in the interface for delivering a read data strobe signal from the peripheral devices. The interface includes a data bus for delivering command, address, and data information. The read data strobe indicates when valid data is present on the data bus. |
