发明名称
摘要 Provided is a storage subsystem capable of maintaining the reliability of I/O processing to a host apparatus, even if there is an unauthorized access from a processor core to a switch circuit, by applying a multi-core system to a processor. A multi-core processor is applied to a second logical address space that is different from a first logical address space to be commonly applied to multiple controlled units such as a host interface to be accessed by the processor. The switch circuit determines the processor core that issued an access based on an address belonging to a second address space, and maps an address containing in an access from the processor core to an address of a first address space.
申请公布号 JP5318223(B2) 申请公布日期 2013.10.16
申请号 JP20110537756 申请日期 2009.04.06
申请人 发明人
分类号 G06F3/06 主分类号 G06F3/06
代理机构 代理人
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