| 摘要 |
A method for manufacturing a thin film transistor array substrate is provided to reduce the width of a semiconductor layer tail exposed to the outside of the data wiring by performing an etching process using a double-stepped photoresist pattern of a double step when forming a data wiring. A gate electrode(101a) and a gate wiring are formed on a substrate(100). A gate insulating layer(104), an amorphous silicon layer, and a third conductive layer are successively formed on the substrate with the gate electrode and the gate wiring. First and second photoresist patterns(102b) are formed on the metal layer by using a diffraction exposure mask. The source/drain electrode pattern and a data wiring pattern are formed by etching the metal layer in the first etching through the first and second photoresist patterns. A third photoresist pattern and a fourth photoresist pattern are formed by ashing the first and second photoresist patterns. A first semiconductor layer under the source/drain electrode pattern and a second semiconductor layer(106c) under the data wiring pattern are formed by etching the semiconductor layer as the second etching. |
