| 摘要 |
<p>A first differential encoding circuit is configured to perform a differential encoding on n-lines parallel input data to generate n-lines parallel output data. A second differential encoding circuit is configured to perform a differential encoding on n-lines parallel input data to generate n-lines parallel output data. A multiplexing circuit is configured to alternately multiplex the generated parallel output data from the first differential encoding circuit and the second differential encoding circuit, and configured to output the multiplexed data.</p> |
