发明名称 |
Low power retention random access memory with error correction on wake-up |
摘要 |
Solid-state random access memory including error correction capability applied to memory arrays entering and exiting a data retention mode. Error correction coding of the data to be retained is performed upon determining that a portion of the memory is to enter data retention mode; the parity bits (i.e., bits in addition to those required for storage of the payload) are stored in available memory cells within or external to the retention domain. Upon exit from retention mode, the code words are decoded to correct any errors, and the payload data are returned to the original cells. Error correction encoding and decoding is not performed in the normal operating mode.
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申请公布号 |
US8560931(B2) |
申请公布日期 |
2013.10.15 |
申请号 |
US201213483897 |
申请日期 |
2012.05.30 |
申请人 |
SESHADRI ANAND;LOH WAH KIT;TEXAS INSTRUMENTS INCORPORATED |
发明人 |
SESHADRI ANAND;LOH WAH KIT |
分类号 |
G06F11/00;G11C5/14;H03M13/00 |
主分类号 |
G06F11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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