发明名称 Low latency inter-die trigger serial interface for ADC
摘要 A packaged controller for closed-loop control applications includes two dies packaged together in a semiconductor package. The first die is optimized for digital circuitry and includes a processor, an ADC, a serial bus interface, and a sequencer. The second die is optimized for analog circuitry and includes a serial bus interface, a plurality of sample/hold circuits, and an analog multiplexer. The sequencer on the first die causes a series of multi-bit values to be communicated serially across a low latency serial bus to the second die, and thereby controls the analog multiplexer and the asserting of a sample/hold signal on the second die. Under control of the sequencer, multiple voltages are captured simultaneously on the second die, and then are multiplexed one by one to the ADC on the first die for conversion into digital values. The architecture reduces complexity and cost of the overall packaged controller.
申请公布号 US8558582(B1) 申请公布日期 2013.10.15
申请号 US201313915606 申请日期 2013.06.11
申请人 ACTIVE-SEMI, INC. 发明人 HSU TSING
分类号 G11C27/02;H03K5/00;H03K17/00 主分类号 G11C27/02
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