| 摘要 |
At least one target metric is identified for an integrated circuit chip design for which manufacturing chip testing is to be optimized. At least one surrogate metric is also identified for the integrated circuit chip design for which manufacturing chip testing is to be optimized. A relationship between the at least one target metric and the at least one surrogate metric is modeled using a general joint probability density function. A chip disposition criterion is determined based on the general joint probability density function. The chip disposition criterion determines, for a given physical chip putatively manufactured in accordance with the design, based on the at least one surrogate metric for the given physical chip, whether the given physical chip is to be accepted or discarded during the manufacturing chip testing.
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