发明名称 Passivation layer for packaged chip
摘要 The embodiments described above provide mechanisms for forming metal bumps on metal pads with testing pads on a packaged integrated circuit (IC) chip. A passivation layer is formed to cover the testing pads and possibly portions of metal pads. The passivation layer does not cover surfaces away from the testing pad region and the metal pad region. The limited covering of the testing pads and the portions of the metal pads by the passivation layer reduces interface resistance for a UBM layer formed between the metal pads and the metal bumps. Such reduction of interface resistance leads to the reduction of resistance of the metal bumps.
申请公布号 US8558229(B2) 申请公布日期 2013.10.15
申请号 US201113313747 申请日期 2011.12.07
申请人 JENG SHIN-PUU;WU WEI-CHENG;HOU SHANG-YUN;YU CHEN-HUA;LIU TZUAN-HORNG;CHIU TZU-WEI;HSU KUO-CHING;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 JENG SHIN-PUU;WU WEI-CHENG;HOU SHANG-YUN;YU CHEN-HUA;LIU TZUAN-HORNG;CHIU TZU-WEI;HSU KUO-CHING
分类号 H01L23/58 主分类号 H01L23/58
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