| 摘要 |
This technique relates to a data processing device and a data processing method that allows tolerance against data errors to be improved. When an LDPC code having a DVB-S.2 code length of 16,200 bits and a coded rate of 1/3 is modulated at 16 QAM, a demultiplexor performs a rearrangement in which, e.g., b0, b1, b2, b3, b4, b5, b6, and b7 are reassigned to y6, y0, y3, y4, y5, y2, y1, and y7, respectively, where bit b#i represents the (i+1)th of 4×2 code bits and bit y#i represents the (i+1)th of 4×2 symbol bits for two consecutive symbols, counting in both cases from the most significant bit. The present invention can be applied, e.g., to a transmission system or the like for transmitting LDPC codes. |
