发明名称 |
SEMICONDUCTOR MEMORY AND METHOD OF OPERATING SEMICONDUCTOR MEMORY |
摘要 |
<p>PURPOSE: A semiconductor memory device and an operating method of the semiconductor memory device improve cell holding characteristics by controlling a reference potential to be low. CONSTITUTION: A first precharge circuit (16-1) couples a reference potential generating circuit (12) with a first bit line pair to precharge the first bit line pair to a reference potential. A first equalizer circuit equalizes the first bit line pair. A first sense amplifier is coupled to the first bit pair to amplify a voltage difference of the first bit line pair during activation. A second sense amplifier is coupled to a second bit line pair to amplify a voltage difference of the second bit line pair during activation. [Reference numerals] (12) Reference potential generating circuit; (13) Dummy bit line potential generating circuit; (AA) Reference potential controlling circuit</p> |
申请公布号 |
KR20130111377(A) |
申请公布日期 |
2013.10.10 |
申请号 |
KR20130032701 |
申请日期 |
2013.03.27 |
申请人 |
RENESAS ELECTRONICS CORPORATION |
发明人 |
TAKAHASHI HIROYUKI |
分类号 |
G11C7/10;G11C5/14;G11C7/06 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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