Technique for optimization and re-use of hardware in the implementation of instructions used in viterbi and turbo decoding, using carry and save arithmetic

摘要

The present invention provides a means for optimization and re-use of hardware in the implementation of Viterbi and Turbo Decoders using carry save arithmetic. Successful provision for each target application requires that two main issues be confronted. These are: merging the computation of summation terms (a2-b2+c2) with (x2+y2+z2); and (a3+b3-c3) with (x3+y3+z3); implementing an efficient method of computing (a4-b4-c4); and merging this computation with (x4+y4+z4). The invention solves both of these issues and successfully merges the Viterbi instructions with a complete reuse of the hardware that is required for the implementation of Turbo instructions. The hardware required by both classes of instructions is optimized by efficiently employing carry save arithmetic.