| 摘要 |
A clock data restoration device (1A) includes a sampler portion (11), a phase comparison portion (12), a drive portion (13), a charge pump (14), a capacitive element (15), a potential adjustment portion (16) and a voltage control oscillator (17). The phase comparison portion (12) outputs a signal (UP) that becomes a significant value when the phase of a clock (CKX) delays with respect to an input digital signal, and outputs a signal (DN) that becomes a significant value when the phase advances. The drive portion (13) increases or decreases a value delta to or from a variable Delta when the signals (UP) and (DN) become a significant value, and increases or decrease a value N to or from the variable Delta when the value of the variable Delta is equal to or more than +N or when the value of the variable Delta is equal to or less than -N, and signals (UPFRQ) and (DNFRQ) are output to the charge pump (14). The potential adjustment portion (16) increases or decreases a potential at a first end of a capacitive element (15) based on the signals (UP) and (DN).
|
