| 摘要 |
<p>The present invention addresses the issue of reducing parasitic capacitance between gate wiring and a substrate, and providing a surrounding gate transistor (SGT) manufacturing method, which is a gate-last process, and a structure of the SGT obtained as a result of employing the method. The issue is solved by means of: a step wherein a fin-like silicon layer is formed on a silicon substrate, a first insulating film is formed at the periphery of the fin-like silicon layer, and a columnar silicon layer is formed on an upper portion of the fin-like silicon layer; a step wherein, after the previous step, a diffusion layer is formed by injecting an impurity into an upper portion of the columnar silicon layer, the upper portion of the fin-like silicon layer, and a lower portion of the columnar silicon layer; a step wherein, after the previous step, a gate insulating film, a polysilicon gate electrode and polysilicon gate wiring are formed; a step wherein, after the previous step, a silicide is formed on an upper portion of the diffusion layer on the upper portion of the fin-like silicon layer; a step wherein, after the previous step, an interlayer insulating film is deposited, the polysilicon gate electrode and the polysilicon gate wiring are exposed, the polysilicon gate electrode and the polysilicon gate wiring are etched, then, a metal is deposited, and a metal gate electrode and metal gate wiring are formed; and a step wherein, after the previous step, a contact is formed.</p> |
