| 摘要 |
A memory array includes: at least one differential local bit line pair; at least one differential global bit line pair; at least a column selection signal, for charging the differential local bit line pair to a predetermined voltage; at least an enable signal for coupling the differential local bit line pair to the differential global bit line pair when a voltage of the differential local bit line pair reaches a specific value; and a local sense accelerator, coupled to the differential local bit line pair, for determining a voltage of the differential local bit line pair, and enabling an accelerator signal for latching one of the differential local bit line pair and pulling the other low when the voltage reaches the specific value.
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