发明名称 DELAY ADJUSTMENT DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a delay adjustment device for use with semiconductor elements connected in parallel which matches output timings without increasing switching loss.SOLUTION: Line length adjustment elements 1 each having a metal pattern 4 formed in a high dielectric constant material 3 are used to delay a gate signal to the semiconductor elements connected in parallel. This can match output timings without increasing switching loss.
申请公布号 JP2013207309(A) 申请公布日期 2013.10.07
申请号 JP20120070490 申请日期 2012.03.27
申请人 PANASONIC CORP 发明人
分类号 H03K5/14;H01P9/00 主分类号 H03K5/14
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