发明名称 SAMPLE HOLD CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a sample hold circuit having excellent noise characteristics, not influenced by a variation of input common voltage, and preventing a gain error.SOLUTION: Differential input signals VIP, VIN are connected to respective ends of sampling capacitors C1, C2 in a sample phase. Dummy capacitors CPP2, CPN2 are provided each of which has a capacity equal to corresponding capacities of the parasitic capacitance CPP1, CPN1 of an input terminal of a differential operational amplifier 11. An input signal having opposite polarity of the sampling capacitors C1, C2 is sampled.
申请公布号 JP2013207696(A) 申请公布日期 2013.10.07
申请号 JP20120077090 申请日期 2012.03.29
申请人 ASAHI KASEI ELECTRONICS CO LTD 发明人 MATSUURA RYO
分类号 H03M1/12 主分类号 H03M1/12
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