发明名称 ENCODER SIGNAL PROCESSING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide an encoder signal processing circuit capable of preventing erroneous counting from being performed even when a noise signal such as mechanical fine vibration in the stopped state of a rotary encoder and preventing accumulation of shifting of count values.SOLUTION: An encoder signal processing circuit includes a circuit for generating an A-phase pulse of clock synchronization and a B-phase pulse of clock synchronization, a 4-multiplication pulse generation circuit for generating rising edge signals and falling edge signals of the A-phase pulse and the B-phase pulse of the clock synchronization, and generating a 4-multiplication pulse from the rising edge signals and the falling edge signals, an alternate checking circuit for generating a signal indicating the stop period of an encoder on the basis of whether the A-phase pulse and the B-phase pulse of the clock synchronization have been alternately input, and a circuit for generating a noise-removed 4-multiplication pulse signal from the 4-multiplication pulse during a period other than the encoder stop period.
申请公布号 JP2013205073(A) 申请公布日期 2013.10.07
申请号 JP20120071353 申请日期 2012.03.27
申请人 TOPPAN PRINTING CO LTD 发明人 FUJIWARA YUTAKA
分类号 G01D5/244 主分类号 G01D5/244
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