发明名称 |
SEMICONDUCTOR DEVICE AND OPERATION TIMING ADJUSTMENT METHOD THEREFOR |
摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor device capable of accurately adjusting timing at which an input circuit captures data.SOLUTION: An interface chip IF has a TSV buffer 52 that serially outputs a plurality of write data items to a core chip CC0 at timing based on a control signal DWCLKTSV. The core chip CC0 includes: holding circuits 70a and 70b that parallelly hold the write data items which are serially supplied from the interface chip IF; a write control timing adjustment circuit 76 that generates a control signal DWCLKTSVOUT according to an internal write command WR; a delay adjustment circuit 75 that delays the timing for supplying the internal write command WR to the write control timing adjustment circuit 76; and an input buffer 71 that sequentially retrieves the plurality of write data items from the holding circuits 70a and 70b at the timing based on the control signal DWCLKTSVOUT. |
申请公布号 |
JP2013206255(A) |
申请公布日期 |
2013.10.07 |
申请号 |
JP20120075992 |
申请日期 |
2012.03.29 |
申请人 |
ELPIDA MEMORY INC;HITACHI ULSI SYSTEMS CO LTD |
发明人 |
IDE AKIRA;OGAWA NAOKI |
分类号 |
G06F12/00;G11C11/401 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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