发明名称 LOGIC VERIFICATION SYSTEM AND PROGRAM
摘要 PROBLEM TO BE SOLVED: To provide technology capable of reducing time for test and verification related to a logic verification system.SOLUTION: A logic verification system comprises: a random number test data generation part 101 for generating random number test data on the basis of test condition information 102 and 110; a logical simulator 103 for performing logical simulation of logic to be simulated by inputting the random number test data, and outputting coverage information; a coverage determining part 105 for performing determination processing of variation of coverage when testing by using coverage output and coverage storage information, and storing test condition information corresponding to a part where the coverage is improved as test condition storage information (106); and an additional test condition generation determining part 108 for determining whether it is necessary that an additional test condition (110) must be generated by using test condition generation determining information (109), and generating and storing the additional test condition information (110).
申请公布号 JP2013200662(A) 申请公布日期 2013.10.03
申请号 JP20120067965 申请日期 2012.03.23
申请人 HITACHI INFORMATION & TELECOMMUNICATION ENGINEERING LTD 发明人 HISATOMI YASUOKI;SUNADA KUNIO;UNNO KOICHI
分类号 G06F17/50;G01R31/28;G01R31/3183 主分类号 G06F17/50
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