发明名称 |
D/A CONVERTER AND JITTER FREQUENCY CONTROL CIRCUIT |
摘要 |
PROBLEM TO BE SOLVED: To provide a D/A converter that reduces effects of noise on electronic components.SOLUTION: The D/A converter includes: a sampling circuit 160 having a sample-and-hold section 150b for sampling an input signal based on a digital signal input by a digital section 150c and holding and transferring the sampled signal, and a continuous section 150a for outputting the signal transferred by the sample-and-hold section as an analog signal; a clock signal generation section 143 for generating a clock signal &phgr;1' supplied to the sample-and-hold section 150b and a clock signal &phgr;2 supplied to the continuous section 150a; a jitter generation section 141 for generating jitter added to at least the clock signal &phgr;1'; and a jitter frequency control circuit 171 for controlling the frequency of the jitter generated by the jitter generation section 141. |
申请公布号 |
JP2013201487(A) |
申请公布日期 |
2013.10.03 |
申请号 |
JP20120067153 |
申请日期 |
2012.03.23 |
申请人 |
ASAHI KASEI ELECTRONICS CO LTD |
发明人 |
NAKANISHI JUNYA;NAKANISHI YUTAKA |
分类号 |
H03M1/08 |
主分类号 |
H03M1/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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