发明名称 |
DUAL-PORT SRAM WITH BIT LINE CLAMPING |
摘要 |
In one embodiment, a memory includes a plurality of bit lines and a write driver for driving a driven bit line selected from the plurality of bit lines during a write operation. The write driver is coupled to an internal node. A first stage clamping circuit is operable to clamp the internal node to a clamping voltage if the write operation is not enabled and is further operable to unclamp the internal node during the write operation. The memory further includes a multiplexer for selectively coupling the driven bit line to the internal node. A second stage clamping circuit is operable to clamp the plurality of bit lines to a clamping voltage if the write operation is not enabled and is further operable to unclamp the driven bit line during the write operation.
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申请公布号 |
US2013258761(A1) |
申请公布日期 |
2013.10.03 |
申请号 |
US201313901853 |
申请日期 |
2013.05.24 |
申请人 |
LATTICE SEMICONDUCTOR CORPORATION |
发明人 |
SHARPE-GEISLER BRAD;SWENSEN TIMOTHY SCOTT;TSAI SAM;FONTANA FABIANO |
分类号 |
G11C11/419 |
主分类号 |
G11C11/419 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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