发明名称 INTER-DIE CONNECTION WITHIN AN INTEGRATED CIRCUIT FORMED OF A STACK OF CIRCUIT DIES
摘要 An integrated circuit is formed of a plurality of circuit dies 22, 24 having through silicon vias (TSVs) passing there-through. The placement patterns of the through silicon vias differ between the circuit dies. An inter-die routing layer is provided either in a face of a substrate of one of the circuit dies or in an outer face of a layer of processing circuitry of one of the circuit dies. The inter-die routing layer bridges the gaps between the vias and the connection points of different circuit dies. The inter-die routing layer may be formed of metal tracks.
申请公布号 US2013256908(A1) 申请公布日期 2013.10.03
申请号 US201013992399 申请日期 2010.12.13
申请人 MCLAURIN TERESA LOUISE;ARM LIMITED 发明人 MCLAURIN TERESA LOUISE
分类号 H01L25/065;H01L21/50 主分类号 H01L25/065
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