发明名称 TIME TO DIGITAL CONVERTER AND CONTROL METHOD
摘要 <p>A first switching unit (101) can switch between a first state in which a first clock signal (Signal) input from a first input pin (IN1) is input to a first delay element (C11), and a second state in which an output signal of a second delay element (C2N) is input. A second switching unit (102) can switch between a first state in which a second clock signal (Ref CLK) input from a second input pin (IN2) is input to a second delay element (C21), and a second state in which an output signal of a first delay element (C1N) is input. A controller (701) sets the first and second switching units to the second state after the two clock signals have been incorporated into the first delay elements (C11-C1N) and the second delay elements (C21-C2N) respectively by setting the first and second switching units (101, 102) to the first state. An output unit (OUT) decodes values stored in FFs (710-71N) in the second state and outputs the obtained phase shift.</p>
申请公布号 WO2013145136(A1) 申请公布日期 2013.10.03
申请号 WO2012JP58008 申请日期 2012.03.27
申请人 FUJITSU LIMITED;CHAIVIPAS, WIN;MATSUDA, ATSUSHI 发明人 CHAIVIPAS, WIN;MATSUDA, ATSUSHI
分类号 H03M1/12 主分类号 H03M1/12
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