| 摘要 |
Deterioration of holding characteristics due to fluctuations in power supply voltage VDD is prevented. During ting ending in one of memory circuits, a pair of bit lines in the other memory circuit is controlled to a dummy-bit-line voltage ranging from a ground voltage to ½×VDD. In a subsequent precharge period, a pair of bit lines in one of the memory circuits and the pair of bit lines in the other memory circuit are coupled to a reference voltage generating circuit.
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