| 摘要 |
Low-power, easily scalable architectures for high-speed data handling are critical to modern circuits and systems. Successful architectures must provide efficient data storage and efficient/flexible data retrieval with low power consumption. Data encoding, including that achieved with turbo codes, have data streams split into a sequence of even and odd data bits. These bits are written into multiple single-port memories so that the writing alternates between memories. Scheduling for the reading and writing is performed to avoid conflicts and give priority to the read operations.
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