| 摘要 |
<p>The objective is to provide a semiconductor memory device capable of stable operation without design margins independent of the design dimensions of each transistor forming the circuit. The configuration provides a memory cell (1) equipped with a D-latch circuit (2) that has a D terminal (D), a clock terminal (phi), and a Q terminal (Q_), passes the voltage of a data signal of a D terminal (D) from a bit line when a write selection signal of the clock terminal (phi) is asserted, holds the voltage of a data write data signal when a write selection signal is negated, and outputs the inverted value of the through/hold voltage from the Q terminal (Q_), and a tri-state buffer (3) that is connected between the Q terminal (Q_) of the D latch circuit (2) and the data line (D), outputs the inverted value of the voltage of the Q terminal (Q_) to the bit line (D) when a read selection signal is asserted, and sets the output to the high impedance state when the read selection signal is negated.</p> |
