Integrated circuits with multi-stage logic regions

摘要

A programmable logic region (28) on a programmable integrated circuit may include a first set (34) of look-up tables (A, C) that receive programmable logic region input signals and a second set (38) of look-up tables (B, D) that produce programmable logic region output signals. Multiplexer circuitry (40) may be interposed between the first (34) and second sets (38) of look-up tables (A, B, C, D). The multiplexer circuitry (36) may receive the programmable logic region input signals in parallel with the output signals from the first set of look-up tables (A, C) and may provide corresponding selected signals to the second set of look-up tables (B, D). The programmable logic region input signals may be shared by the first and second sets of look-up tables. Logic circuitry may be coupled to outputs of the first and second sets of look-up tables. The logic circuitry may be configured to logically combine output signals from the first and second sets of look-up tables.