| 摘要 |
A method and apparatus for a memory bus interface including a read data strobe. The interface includes a chip select 215, CS# for delivering a chip select signal (CS# figure 3B) that indicates when a peripheral device (135, figure 1) is activated, wherein the bus interface 210 provides communication between a host device (106 figure 1) and the peripheral device (135 figure 1). The interface also includes a differential clock pair 223 (CK) , 225, (CK#), for delivering a differential clock signal (CK,CK# figure 3B). A read data strobe 230, RDS is included in the interface for delivering a read data strobe signal from the peripheral device (RDS figure 3B). The interface includes a data bus 235, DQ[7-0], for delivering command, address, and data information. The read data strobe indicates when valid data is present on the data bus. The pair of differential clocks and the read data strobe enable transfer of data in a Double Data Rate (DDR) manner. The functionality of the clock pair and also the read data strobe may be single ended or differential. The pin count is therefore reduced having an twelve (12) line interface which comprises an eight (8) line wide data bus. |
