发明名称 DRAM and memory array
摘要 A dynamic random access memory (DRAM) includes a substrate, a plurality of bit lines, a plurality of word lines, a plurality of recess channels, a plurality of conductive plugs and a plurality of trench capacitors. In the DRAM, the bit lines are disposed on the substrate in a first direction, and the word lines are disposed on the bit lines in a second direction. Each recess channel is in the substrate between two bit lines below the word line, and each conductive plug connects each recess channel and the word lines. Each trench capacitor is disposed in the substrate between two bit lines where the recess channels are not formed. Because the word lines can be electrically connected with the recess channels directly without using an additional chip area, the WL access time can be accelerated without an increase of the chip size.
申请公布号 US8547729(B2) 申请公布日期 2013.10.01
申请号 US20080191315 申请日期 2008.08.14
申请人 HUANG WEN-KUEI;NANYA TECHNOLOGY CORPORATION 发明人 HUANG WEN-KUEI
分类号 G11C11/24 主分类号 G11C11/24
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