发明名称 |
Replacement metal gate processing with reduced interlevel dielectric layer etch rate |
摘要 |
A method of forming a semiconductor device structure includes forming an interlevel dielectric (ILD) layer over a semiconductor substrate and a dummy transistor gate structure formed on the substrate; infusing a shallow gas cluster ion beam (GCIB) layer in a top portion of the ILD layer; and removing at least one layer from the dummy transistor gate structure, wherein the at least one layer comprises a same material as the ILD layer and wherein the GCIB layer has a slower etch rate with respect to the ILD layer.
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申请公布号 |
US8546209(B1) |
申请公布日期 |
2013.10.01 |
申请号 |
US201213524576 |
申请日期 |
2012.06.15 |
申请人 |
CHENG KANGGUO;WANG JUNLI;WONG KEITH KWONG HON;YANG CHIH-CHAO;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CHENG KANGGUO;WANG JUNLI;WONG KEITH KWONG HON;YANG CHIH-CHAO |
分类号 |
H01L21/338 |
主分类号 |
H01L21/338 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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