发明名称 |
Architecture for high speed serial transmitter |
摘要 |
A system provides for a serial transmitter with multiplexing and driving functionality that is combined into a single stage to increase the overall speed of the serial transmitter. The single stage includes a dynamic impedance that is configured in parallel with a multiplexing driver to reduce the input capacitance and set the correct output impedance. The single stage can be implemented as a stacked or cross-coupled XOR logic circuit or a stacked or cross-coupled multiplexer ("mux") as the multiplexing driver. In an embodiment where a mux is used as the multiplexing driver, a clock can be injected into the mux driver to overcome inter-symbol interference.
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申请公布号 |
US8547134(B1) |
申请公布日期 |
2013.10.01 |
申请号 |
US201213556381 |
申请日期 |
2012.07.24 |
申请人 |
ZAFRA-PETERSSON AXEL;MANSSON JOHAN H.;ELLIOTT MICHAEL R.;JEFFRIES BRAD P.;ANALOG DEVICES, INC. |
发明人 |
ZAFRA-PETERSSON AXEL;MANSSON JOHAN H.;ELLIOTT MICHAEL R.;JEFFRIES BRAD P. |
分类号 |
H03K17/16;H03B1/00;H03K3/00;H03K19/003;H03K19/094 |
主分类号 |
H03K17/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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