发明名称 |
System and method for reducing latency associated with timestamps in a multi-core, multi-threaded processor |
摘要 |
A system and method are provided for reducing a latency associated with timestamps in a multi-core, multi threaded processor. A processor capable of simultaneously processing a plurality of threads is provided. The processor includes a plurality of cores, a plurality of network interfaces for network communication, and a timer circuit for reducing a latency associated with timestamps used for synchronization of the network communication utilizing a precision time protocol.
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申请公布号 |
US8549341(B2) |
申请公布日期 |
2013.10.01 |
申请号 |
US20080201689 |
申请日期 |
2008.08.29 |
申请人 |
SHAHID AHMED;KUILA KAUSHIK;HASS DAVID T.;NETLOGIC MICROSYSTEMS, INC. |
发明人 |
SHAHID AHMED;KUILA KAUSHIK;HASS DAVID T. |
分类号 |
G06F1/00 |
主分类号 |
G06F1/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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