发明名称 SEMICONDUCTOR DEVICE MANUFACTURING METHOD
摘要 PROBLEM TO BE SOLVED: To solve a problem that a short margin is not likely to be ensured when a clearance of an upper part of a hole is widened by etch back.SOLUTION: A semiconductor device manufacturing method comprises: a process of depositing a first interlayer insulation film on a predetermined member; a process of depositing on the first interlayer insulation film, a second interlayer insulation film having an etching rate lower than that of the first interlayer insulation film; a process of depositing a support insulation film having an etching rate lower than an etching rate of the first interlayer insulation film and an etching rate of the second interlayer insulation film; a process of depositing on the support insulation film, a sacrificial film having a wet etching rate higher than an etching rate of the first interlayer insulation film and an etching rate of the second interlayer insulation film; a process of forming a cylinder hole leading to a pad from the sacrificial film to the first interlayer insulation film by a lithography technique and anisotropic etching; and a process of selectively wet etching a surface of the first interlayer insulation film and removing the sacrificial film at the cylinder hole with respect to the second interlayer insulation film.
申请公布号 JP2013197527(A) 申请公布日期 2013.09.30
申请号 JP20120066171 申请日期 2012.03.22
申请人 ELPIDA MEMORY INC 发明人 SUGIOKA SHIGERU
分类号 H01L21/8242;H01L27/108 主分类号 H01L21/8242
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