发明名称 DESIGN SUPPORT DEVICE OF SEMICONDUCTOR INTEGRATED CIRCUIT AND FALSE PATH EXTRACTION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a design support device of a semiconductor integrated circuit and a false path extraction method of the semiconductor integrated circuit, capable of automatically extracting a timing exception path whose start point is a register with no value change, and reducing the time and labor needed for preparation of an SDC file.SOLUTION: A toggle determination part 15 determines presence/absence of the change of a value of a register on the basis of an RTL source 21 and a test pattern 22, a coverage analysis part 14 calculates block coverage on the basis of the RTL source 21 and the test pattern 22, and a false path determination part 18 selects the register with no value change in the toggle determination part 15, determines, as a false path, a route whose start point is the register positioned (provided) in the preceding stage of the register selected in a logic cone extraction part 16, which is also the register for which the coverage analysis part 14 has calculated that the block coverage is 100% in the coverage determination part 17, and outputs it as an SDC file.
申请公布号 JP2013196132(A) 申请公布日期 2013.09.30
申请号 JP20120060397 申请日期 2012.03.16
申请人 RICOH CO LTD 发明人 KUMANO YOSHINORI
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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