发明名称 CLOCK GENERATING DEVICE AND INFORMATION PROCESSING APPARATUS
摘要 PROBLEM TO BE SOLVED: To suppress power consumption by maintaining a synchronous relation between LRCLK and BCLK while using a low-frequency system clock.SOLUTION: A clock generating device comprises first clock generating means which generates a first clock from a system clock, second clock generating means which generates a second clock of a higher frequency than a frequency of the first clock from the system clock, count means which counts the number of second clocks included within a term of the first clock, and adjustment means which adjusts a falling edge or a rising edge of the second clock to be synchronized with a falling edge or a rising edge of the first clock based on an assert signal which is outputted when a count value obtained by the count means becomes a predetermined value.
申请公布号 JP2013196380(A) 申请公布日期 2013.09.30
申请号 JP20120062789 申请日期 2012.03.19
申请人 RICOH CO LTD 发明人 FUKUSHIMA KOYO
分类号 G06F1/12;H03K5/00;H03K5/26 主分类号 G06F1/12
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