| 摘要 |
PROBLEM TO BE SOLVED: To provide a processor system for efficiently switching the validity and invalidity of error correction processing.SOLUTION: The processor system includes: an instruction decode part 11 for decoding an instruction fetched by an instruction fetch control part 10, and for generating an arithmetic instruction and a program count value corresponding to the arithmetic instruction; an arithmetic execution part 12 for executing an arithmetic operation based on the arithmetic instruction; a specific code area determination part 16 for, when the program count value corresponding to the arithmetic instruction is within the range of a specific code area, setting a specific code area determination signal to an enable state; and a bus control part 15 for performing transmission/reception of data with another device via a system bus. The bus control part 15 switches whether to simplify error correction processing to be performed to at least either an address showing an address destination or data in accordance with the specific code area determination signal. |
