| 摘要 |
A capacitor-less dynamic semiconductor memory device and a method of operating the same are provided to reduce layout area by simplifying circuits to generate a reference voltage. Memory cells comprise floating body transistors having gates connected to a word line, drains connected to a plurality of bit lines and sources connected to a plurality of source lines. A first dummy cell(DC0) stores data 1, and has a floating body transistor having a gate connected to the word line, a drain connected to a first dummy bit line and a source connected to a first dummy source line. A second dummy cell(DC1) stores data 0, and has a gate connected to the word line, a drain connected to a second dummy bit line and a source connected to a second dummy source line. An equalizing transistor equalizes the first dummy bit line and the second dummy bit line in response to an equalizing signal. A bit line selector(321-2) connects one of the plurality of bit lines to a sensing bit line in response to a bit line selection signal. A dummy bit line connection part(331-1,331-2) connects one of the first and dummy bit lines to an inverted sensing bit line in response to each of first and second dummy bit line selection signals. A sensing part(340-1,340-2) senses and amplifies voltage difference between the sensing bit line and the inverted sensing bit line. |
