发明名称 CONTROLLED AREA SOLDER BONDING FOR DIES
摘要 PROBLEM TO BE SOLVED: To provide a method for solder bonding which accurately controls a bonding area, a thickness and a shape etc. to reduce die stress.SOLUTION: A method of fabricating a semiconductor comprises: forming a plurality of stud bumps in a pattern having a geometrical shape on a surface of a substrate, the pattern defining a periphery of a bonding area on the surface of the substrate 118; and placing a solder material 120 in the bonding area such that the solder material 120 is surrounded by the stud bumps 110. The solder material is heated to a temperature where the solder material begins to flow within the bonding area. A bonding surface of a die 130 is pressed onto the stud bumps with a sufficient pressure to crush the stud bumps to a predetermined extent such that the solder material substantially evenly spreads between the stud bumps within the bonding area. The solder material is then solidified to form a final solder area that conforms to the geometrical shape of the pattern of stud bumps.
申请公布号 JP2013191847(A) 申请公布日期 2013.09.26
申请号 JP20130048932 申请日期 2013.03.12
申请人 HONEYWELL INTERNATL INC 发明人 ESKRIDGE MARK
分类号 H01L21/52;H01L21/60 主分类号 H01L21/52
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