| 摘要 |
PROBLEM TO BE SOLVED: To provide a bus circuit for completing transfer in each transfer packet within a targeted time.SOLUTION: A bus circuit 20 for connecting a plurality of masters 10A to 10C and a plurality of slaves 11a to 11c such that the plurality of masters 10A to 10C access the plurality of slaves 11a to 11c, respectively in outstanding and out-of-order manners has a plurality of interfaces 30A to 30C for a master, a plurality of interfaces 40a to 40c for a slave, a switch 50 for switch connections, a configuration register 71 for storing a setting item relating to a time requested in data transfer, and a timer 72 for measuring a time elapse in data transfer. In the bus circuit, the switch switches the connections so as to satisfy the setting item stored in the configuration register on the basis of the time elapse measured by the timer. |
