| 摘要 |
A memory cell array including a plurality of memory cell units arrayed in a matrix configuration along a first direction and a second direction which is perpendicular direction to the first direction, each memory cell unit including a plurality of memory cell transistors, a first select gate transistor and a second select gate transistor, word lines extending to the first direction, and a first insulating film formed on an upper surface of the memory cell array, a first embedded wiring layer embedded in the first embedded wiring layer, the first embedded wiring layer including a wiring portion commonly connected to a source region of each first select gate transistor, wherein the first embedded wiring layer has an inclined pattern which extends in a direction not parallel to either of the first and the second directions. |
