| 摘要 |
<p>The present invention relates to a register cell comprising one output node (OUT); at least two power supply nodes (VP, GND); and a first flash transistor (1201) and a second flash transistor (1202); wherein the register cell is configured so that the output node can be driven by at least one of the power supply nodes, as a function of the value stored in at least one of the flash transistors. The invention further relates to a FPGA comprising the register cell.</p> |
