发明名称 OUTPUT CONTROL CIRCUIT, SCAN LINE DRIVE CIRCUIT OF ELECTRO-OPTICAL DEVICE, ELECTRO-OPTICAL DEVICE AND ELECTRONIC APPARATUS
摘要 PROBLEM TO BE SOLVED: To prevent a pulse width of an output signal from being reduced and further to prevent the output signal from being output at an unexpected timing when an enable signal is delayed due to any reason with respect to a pulse signal that is an input signal.SOLUTION: An output control circuit 30 includes a first circuit 30a including a NOT circuit 31(i), a NAND circuit 32(i) and a transmission gate 34(i) as first sub-circuits and a second circuit 30b including a NAND circuit 36(i) as a second sub-circuit. The NAND circuit 32(i) controls transfer of an enable signal Enb-k to the NAND circuit 36(i) by the transmission gate 34(i) on the basis of a signal SR(i) logically inverted by the NOT circuit 31(i) and the NAND circuit 36(i).
申请公布号 JP2013190509(A) 申请公布日期 2013.09.26
申请号 JP20120055389 申请日期 2012.03.13
申请人 SEIKO EPSON CORP 发明人 FUJIKAWA SHINSUKE
分类号 G09G3/36;G02F1/133;G09G3/20 主分类号 G09G3/36
代理机构 代理人
主权项
地址