| 摘要 |
PROBLEM TO BE SOLVED: To provide a cache device capable of reducing power consumption while securing performance.SOLUTION: A cache device according to the embodiment, which is a cache device of an n(n≥2)-way set associative system, includes a cache memory, an access control part, and a power control part. The cache memory has a plurality of memory areas corresponding to a plurality of ways on a one-to-one basis. The access control part controls access to the memory area. The power control part controls power supply for each memory area one by one, and controls, as to a memory area to which access control is not executed for a fixed period of time, a power supplied to the memory area to a standby power indicative of a value lower than an operation power at which the memory area is operable. The power control part also controls a standby power of a memory area to which an access control is highly likely to be performed, to a value closer to an operation power than the standby power of a memory area to which an access control is not likely to be performed. |
