| 摘要 |
According to one aspect of the teachings presented in this document, a wireless communication receiver implements a form of joint detection that is referred to as “fast joint detection” (FJD). A receiver that is specially adapted to carry out FJD processing provides an advantageous approach to joint detection processing wherein the number of computations needed to produce reliable soft bits, for subsequent turbo decoding and/or other processing, is significantly reduced. Further, the algorithms used in the implementation of FJD processing are particularly well suited for parallelization in dedicated signal processing hardware. Thus, while FJD processing is well implemented via programmable digital processors, it also suits applications where high-speed, dedicated signal processing hardware is needed or desired. |
